Journal of Beijing University of Posts and Telecommunications

  • EI核心期刊

JOURNAL OF BEIJING UNIVERSITY OF POSTS AND TELECOM ›› 2007, Vol. 30 ›› Issue (5): 19-23.doi: 10.13190/jbupt.200705.19.niudh

• Papers • Previous Articles     Next Articles

Incremental Sequence Pair Generation Algorithm for SOC Test Scheduling

NIU Dao-heng, WANG Hong, YANG Shi-yuan   

  1. (Department Automation, Tsinghua University, Beijing 100084, China)
  • Received:2006-12-14 Revised:2007-03-28 Online:2007-10-30 Published:2007-10-30
  • Contact: NIU Dao-heng

Abstract:

A deterministic algorithm is proposed for System-on-Chip (SOC) test scheduling. With the optimal assignment and balance design for test wrappers, four types of incremental Sequence Pair generation methods are constructed as a cyclic iteration process. By considering the TAM width, dead space, and test area for IP cores simultaneously, the algorithm can achieve effective solutions in certain iteration steps. Experimental results on ITC’02 benchmark show that the proposed algorithm performs faster than the traditional SA method while obtaining comparable results.

Key words: system-on-chip, test scheduling, test wrapper, test access mechanism, sequence pair

CLC Number: